1. Field of the Invention
The present disclosure generally relates to the formation of semiconductor devices and, more specifically, to various methods of forming gate structures of semiconductor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein so-called metal oxide semiconductor field effect transistors (MOSFETs or FETs) represent one important type of circuit element that substantially determines performance of the integrated circuits. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices.
Field effect transistors, whether an NMOS or a PMOS device, typically have a source region, a drain region, a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. Current flow through the FET is controlled by controlling the voltage applied to the gate electrode. For an NMOS device, if there is no voltage (or a logically low voltage) applied to the gate electrode, then there is no current flow through the device (ignoring undesirable leakage currents, which are relatively small). However, when an appropriate positive voltage (or logically high voltage) is applied to the gate electrode, the channel region of the NMOS device becomes conductive, and electrical current is permitted to flow between the source region and the drain region through the conductive channel region. For a PMOS device, the control voltages are reversed. Field effect transistors may come in a variety of different physical shapes, e.g., so-called planar FET devices or so-called 3D or FinFET devices.
For many early device technology generations, the gate structures of most transistor elements have been made of a plurality of silicon-based materials, such as a silicon dioxide and/or silicon oxynitride gate insulation layer, in combination with a polysilicon gate electrode. However, as the channel length of aggressively scaled transistor elements has become increasingly small, many newer generation devices employ gate structures that contain alternative materials in an effort to avoid the short channel effects which may be associated with the use of traditional silicon-based materials in reduced channel length transistors. For example, in some aggressively scaled transistor elements, which may have channel lengths on the order of approximately 10-32 nm or less, gate structures that are made of a so-called high-k dielectric gate insulation layer (k value of 10 or greater) and one or more metal layers that function as the gate electrode (HK/MG) have been implemented. Such alternative gate structures have been shown to provide significantly enhanced operational characteristics over the heretofore more traditional silicon dioxide/polysilicon gate structure configurations.
In many cases, the metal-containing gate structures are formed by performing well-known replacement gate processing techniques. In general, the replacement gate technique involves forming a sacrificial gate structure (e.g., a silicon dioxide gate insulating layer and a polysilicon gate electrode) and a gate cap layer, followed by forming a protective sidewall spacer adjacent the gate structure. The sacrificial gate structure is eventually removed to define a replacement gate cavity between the spacer. Thereafter, the high-k gate insulating layer and the various layers of metal that will comprise the gate electrode are sequentially deposited in the gate cavity. Excess materials positioned outside of the gate cavity are removed by performing one or more chemical mechanical polishing (CMP) process operations. Next, one or more recess etching processing operations are performed to remove some of the materials within the gate cavity to create a space for the formation of a protective gate cap layer. The gate cap layer is formed by overfilling the recessed cavity with a material, such as silicon nitride, and thereafter performing a CMP process to remove the excess gate cap materials.
In modern device fabrication, transistors having relative short channel lengths and transistors having relatively long channel lengths are formed on the same substrate. Unfortunately, some of the metal materials employed in such metal gate structures, such as tungsten, have different etch characteristics depending upon the channel length of the transistor device, due to differences in grain sizes. Accordingly, during the recess etching process that is performed to make room for the gate cap layer above the replacement metal-containing gate structure, some of the gate structure materials may be inadvertently removed or etched, leading to poor device performance or lower yield. More specifically, etching the gate structures of devices having different channel lengths may result in uneven and inadvertent etching of at least the metal gate materials, such as tungsten or the like, due to the larger grain size and surface area of the metal material in the longer channel devices.
The present disclosure is directed to various methods of forming gate structures of semiconductor devices and the resulting devices that may solve or reduce one or more of the problems identified above.